1. Field of the Invention
The present invention relates to a semiconductor device in which function elements, such as MOS FETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), are formed, and more particularly to a semiconductor device in which power elements are formed.
2. Description of Related Art
FIG. 6 is a perspective view schematically showing a partly cutaway semiconductor device in the prior art in which MOS FETs are formed.
A semiconductor layer 53 is formed on an N−-type region (drain region) 52 formed on one surface of a semiconductor substrate (not shown). A trench 54 is formed to penetrate through the semiconductor layer 53 and reach the surface layer portion of the N−-type region 52. The trench 54 includes a plurality of trenches which are parallel to the semiconductor substrate and extend in two directions intersecting with each other at right angles.
An oxide film 55 is formed along the inner surface of the trench 54. The interior of the trench 54 is filled with a gate electrode 56 made of polysilicon doped with impurities to be electrically conductive (to lower resistance). The semiconductor layer 53 is divided into a plurality of regions by the trench 54, and cells C, each including a single function element (MOS FET), are fabricated from the semiconductor layer 53 divided by the trench 54, and the oxide film 55 and the gate electrode 56 on the periphery.
The semiconductor layer 53 in each cell C includes an N+-type region (source region) 57 formed along the edge of the trench 54, a P+-type base region 58 formed in a region surrounded by the N+-type region 57, and a P−-type region 59 placed between the N+-type region 52 and the N+-type region 57 as well as the base region 58. The base region 58 is doped with impurities at a higher concentration than the other semiconductor portions and thereby has lower resistance.
The base region 58 is formed from the surface of the semiconductor layer 53 to a region deeper than the N+-type region 57. This configuration makes an interval between the base region 58 and the N−-type region 52 narrower than an interval between the N+-type region 57 and the N−-type region 52.
On the semiconductor layer 53 is provided an unillustrated source electrode that is electrically connected to the N+-type region 57 and the base region 58. The source electrode and the gate electrode 56 are electrically isolated by an unillustrated silicon oxide film.
In the semiconductor device 51, for a current to flow between the N−-type region 52 and the N+-type region 57, a channel is formed in the P−-type region 59 at a portion in close proximity to the interface to the oxide film 55 by applying a sufficiently large voltage between the N−-type region 52 and the source electrode (N+-type region 57) and setting the gate electrode 56 at adequate potential.
In a case where the semiconductor device 51 is used as a switching element, when the semiconductor device 51 is turned OFF, a fly-back voltage is generated due to wiring inductance of circuits including the semiconductor device 51, and a current (surge current) I resulted from the fly-back voltage flows through the low-resistance base region 58. Also, the presence of the base region 58 makes it difficult for a parasitic transistor, comprising the N−-type region 52 as the collector, the P−-type region 59 as the base, and the N+-type region 57 as the emitter, to be switched ON.
This configuration can avoid an unwanted event that the MOS FETs (channel-forming regions in the P−-type regions 59) break due to heat generation.
In a case where the base resistance of the P−-type region 59 is high, however, the parasitic transistor is switched ON. A large current then flows through the P−-type region 59 and the P−-type region 59 may possibly break. Even when the parasitic transistor remains OFF, a current does not necessarily flow evenly through the base regions 58 in the respective cells C, and the current I concentrates in a base region 58 having the lowest resistance value. In this case, a large current flows between this particular base region 58 and the N−-type region 52, and breaking occurs where the large current has flown.
FIG. 7 is a perspective view schematically showing another partly cutaway semiconductor device in the prior art in which MOS FETs are formed.
A semiconductor layer 63 is formed on an N−-type region (drain region) 62 formed on one surface of a semiconductor substrate (not shown). The semiconductor layer 63 includes a P−-type region 69 at the bottom (on the side closer to the N−-type region 62) and an N+-type region 67 at the top (on the side farther from the N−-type region 62).
A plurality of trenches 64 are formed to penetrate through the semiconductor layer 63 and reach the surface layer portion of the N−-type region 62. The semiconductor device 61 is of a so-called stripe structure, and the trenches 64 are formed stripe-wise along one direction within a plane parallel to the semiconductor substrate. The semiconductor layer 63 (the P−-type region 69 and the N+-type region 67) is thus divided (partitioned) to stripe-shaped regions extending in the same direction as the trenches 64.
An oxide film 65 is formed on the inner surface of each trench 64. The interior of the trench 64 is filled with a gate electrode 66 made of polysilicon doped with impurities to be electrically conductive (to lower resistance).
A base region 68, which is doped with P-type impurities at a high concentration, is formed in a direction within the plane parallel to the semiconductor substrate perpendicular to the length direction of the trenches 64. The base region 68 is formed from the surface of the semiconductor layer 63 to a region as deep as the surface layer portion of the N−-type region 62. The base region 68 is formed in a region shallower than the depth of the trenches 64, and is partitioned into a plurality of regions by the trenches 64.
On the semiconductor layer 63 is formed an unillustrated source electrode that is electrically connected to the N+-type region 67 and the base region 68. The source electrode and the gate electrodes 66 are electrically isolated by an unillustrated silicon oxide film.
In this semiconductor device 61, too, the current I resulted from the fly-back voltage flows through the low-resistance base region 68. However, because the base region 68 comprises a plurality of regions separated independently, when a large current concentrates in and flows through a base region 68 having the lowest resistance value, breaking occurs in the vicinity of this particular base region 68.
Apart from these semiconductor devices 51 and 61, there has been proposed a semiconductor device in which, in addition to the active cells (MOS FET cells) having the function elements formed inside, diode cells used to selectively flow a surge current are provided within the active region used as the region where the function elements, such as MOS FETs, are formed. Such a semiconductor device is disclosed, for example, in Japanese Patent No. 2988871. In this semiconductor device, one diode cell is provided for an adequate number (for example, eight) of active cells.
The diode cell includes a semiconductor layer (low-resistance region), which is doped with impurities at a high concentration and formed into a region deeper than the gate electrode in the active cell. This configuration allows a current to flow through the diode cell having a low resistance value when the fly-back voltage is applied to the semiconductor device, and the active cell is thereby protected.
However, a plurality of diode cells are placed discretely in the semiconductor device configured as described above, and a current concentrates in and flows through a diode cell having the lowest resistance value. Hence, there is a risk that breaking occurs in the vicinity of a diode cell having a small resistance value.
Even when a current does not concentrate in a particular diode cell, a large number of diode cells need to be provided within the active region for the current to be dispersed efficiently, which relatively lowers a ratio of the active cells that can be formed within the active region. Current-flowing regions (channel regions) per unit area while the semiconductor device stays ON are thus reduced, which in turn increases the ON-resistance.